The quantum computing landscape of 2025 is no longer defined purely by qubit counts or flashy “quantum supremacy” demonstrations. The conversation has shifted toward error suppression, logical qubit performance, and scalability toward fault-tolerance—the benchmarks that will determine which platforms can handle meaningful, real-world workloads in the coming decade. Three quantum chips stand out in this next-generation wave:
- Google’s 105-qubit Willow chip, designed as an error-corrected platform to push surface-code performance into commercially relevant territory.
- IBM’s Heron R2, the latest in IBM’s modular, scalable superconducting roadmap.
- Microsoft’s Majorana-based chips, a radically different approach that promises intrinsic error protection through topological qubits.
These aren’t just engineering experiments. They are testbeds for the architectures, fabrication processes, and control systems that could define the fault-tolerant machines projected to emerge between 2029 and 2033. Each tackles the challenge from a different angle—Google refining and scaling surface codes, IBM doubling down on chip-to-chip modularity, and Microsoft betting on physics itself to protect quantum information.
Benchmarking them requires more than a spec sheet. It means asking how each design performs in error suppression, logical qubit stability, and architectural scalability—and whether they can evolve into viable, commercial quantum systems.
Google’s Willow: 105 qubits with surface-code ambitions
Willow is the successor to Google Quantum AI’s Sycamore-class processors, but its focus is less on raw qubit count and more on logical qubit reliability. It uses superconducting transmon qubits laid out in a 2D grid optimized for the surface code—a widely used error-correction scheme where each logical qubit is encoded into many physical qubits.
What makes Willow significant is its integration of hardware and decoding improvements aimed at reducing the logical error rate below 10⁻³. This threshold is a critical milestone for running longer quantum algorithms without catastrophic error accumulation.
Early benchmarking in 2025 has shown that Willow’s physical qubits achieve two-qubit gate fidelities above 99.8% and readout fidelities near 99.9%. When mapped into a small-distance surface code, Willow has demonstrated a measurable drop in logical error rates as code distance increases—a key validation that error correction is scaling as expected.
The 105-qubit layout also allows for multiple logical qubits to run in parallel, enabling experiments in logical-qubit networking and early-stage algorithm testing in an error-corrected environment. Google’s long-term plan is to tile Willow-class modules into larger lattices, eventually reaching the thousands of physical qubits per logical qubit needed for fault-tolerance.
IBM’s Heron R2: modular superconducting scalability
IBM’s Heron series is part of its quantum modular architecture strategy, where multiple chips are linked together through high-fidelity interconnects to form larger logical processors. The Heron R2 chip, released in 2025, features 133 superconducting qubits with reduced crosstalk and improved coherence times compared to its predecessors.
One of Heron R2’s standout achievements is its integrated cryogenic signal routing, which reduces latency and thermal noise for multi-chip configurations. IBM has already demonstrated chip-to-chip two-qubit gates with fidelities above 99.5%, a major leap toward building distributed surface-code patches across modular systems.
In benchmarking terms, Heron R2’s focus is less on producing single-chip logical qubits and more on ensuring that multi-chip error-corrected systems behave as a coherent whole. This modularity could allow IBM to scale beyond the yield limits of single-chip fabrication, assembling very large quantum processors from smaller, high-yield units.
Heron R2 also serves as a bridge between today’s NISQ devices and IBM’s planned Kookaburra-class systems, which are projected to integrate over 1,000 physical qubits per module and link dozens of modules together by the early 2030s.
Microsoft’s Majorana chips: a topological leap
While Google and IBM refine superconducting approaches, Microsoft is pursuing a radically different qubit based on Majorana zero modes—exotic quasiparticles that can emerge in specially engineered superconducting nanowires.
The allure of Majorana-based topological qubits is that their quantum information is stored non-locally, making them inherently resistant to certain types of noise. In theory, this intrinsic protection could slash the number of physical qubits needed for a given logical qubit—perhaps from thousands down to dozens.
After years of skepticism and mixed experimental results, Microsoft announced in late 2024 that it had demonstrated the braiding of Majorana modes—a key operation for topological quantum computation—on prototype chips. In early 2025, it unveiled a 4-qubit Majorana chip for benchmarking stability and gate operations, with plans to scale to 32 qubits by 2027.
While the current device lags in raw qubit numbers, its potential error-correction overhead advantage could make it a formidable competitor if the physics continues to hold up at scale. Benchmarking here focuses less on surface-code distances and more on measuring topological gap stability and braid fidelity, both of which will determine if Majorana qubits can deliver on their long-promised durability.
Comparing Quantum Chips Error Suppression Performance
When it comes to suppressing errors, the three platforms are at different maturity stages:
- Willow already operates within a surface-code framework, showing logical error rate improvements with increasing code distance—a direct indicator that its error correction scales.
- Heron R2 focuses on ensuring that inter-module gates maintain high fidelity, a prerequisite for running distributed codes that span multiple chips.
- Majorana chips aim to reduce the need for heavy error correction in the first place, but benchmarking is still in early days, with small qubit arrays under test.
From a purely operational standpoint in 2025, Willow’s error-suppressed logical qubits are the most mature. However, if Microsoft’s topological approach scales as theorized, it could leapfrog in efficiency by the 2030s, delivering fault-tolerance with far fewer resources.
Scaling strategies toward the 2030s
Scaling to fault-tolerant machines is where these designs diverge most dramatically:
Google plans to tile many Willow-class modules into a giant 2D lattice, each contributing surface-code patches. This is a well-understood path but comes with high physical-qubit overhead.
IBM envisions multi-chip quantum modules linked by cryogenic interposers, allowing for physically smaller chips with high yield, assembled into massive processors. This modular approach is more flexible in fabrication but requires rock-solid interconnect performance.
Microsoft aims for drastically reduced overhead by building large arrays of Majorana qubits, where each logical qubit might require fewer than 100 physical qubits. If achieved, this would allow much smaller machines to tackle fault-tolerant workloads.
Commercial readiness and timelines
In terms of when these platforms might hit commercial-grade fault-tolerance:
- Google projects that by 2030–2032, Willow’s descendants could deliver thousands of logical qubits for workloads like quantum chemistry and optimization.
- IBM’s roadmap points to early 2030s for large-scale, modular fault-tolerant systems, with Heron R2 as a stepping stone toward the first multi-module error-corrected networks.
- Microsoft’s timeline is more uncertain but potentially disruptive—if topological scaling succeeds, useful fault-tolerance could arrive in the late 2020s to early 2030s with far lower hardware requirements.
The benchmarking challenge
Directly comparing these devices is tricky because they measure progress differently: logical error rates per cycle, interconnect fidelity, and topological gap stability are not apples-to-apples metrics.
That said, all three are moving toward industry-relevant benchmarks—such as running standard quantum algorithms at fixed logical error thresholds—and participating in early discussions on cross-vendor performance standards.
Conclusion:
The Willow, Heron R2, and Majorana chips represent three distinct visions of how to reach the same goal: fault-tolerant quantum computing that can handle mission-critical workloads without constant error-related interruptions.
In 2025, Willow leads in demonstrated error-corrected operation, Heron R2 sets the pace in modular scalability, and Majorana chips hold the promise of drastically reduced overhead. It’s still far too early to declare a winner—but the diversity of approaches strengthens the overall field, ensuring that if one road hits a dead end, others remain open.
As Mattias Knutsson, Strategic Leader in Global Procurement and Business Development, puts it:
“In quantum hardware, diversity is resilience. Betting on multiple architectures isn’t hedging—it’s ensuring that the industry reaches fault-tolerance faster, and with more robust supply and innovation ecosystems. The companies that keep one eye on performance and the other on scalability will define the next decade.”
The next few years will show whether the physics, fabrication, and funding can align to turn these prototypes into the dependable quantum engines of the 2030s. Whichever design emerges on top, the race itself is pushing the boundaries of science and engineering at a pace few could have imagined even five years ago.
